1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor apparatus, and more particularly to the process of manufacturing TFT type Static Random Access Memories (SRAMs) in which resistance to .alpha. rays can be improved by applying capacitors to cell nodes.
2. Description of the Prior Art
Conventional SRAMs have relied in the use of an N-type substrate and P-well structure to create a barrier for reducing charge collection from impingement by .alpha.-particle.
The use of a buried P.sup.+ barrier layer in a P-well has been proposed to reduce the collection charge and soft-error rate.
When the memory cell size is reduced, however, the cell node capacitance becomes smaller and it is hard to store enough charges to compensate the discharge generated by the .alpha.-particle.
As shown in FIGS. 5(a) and (b), the memory cell parasitic node capacitance is plotted against design rules. In FIG. 5(a), the memory cell parasitic node capacitance is indicated at Cn. As shown in FIGS. 6(a), (b) and (c), the memory cell parasitic node capacitance Cn is composed of the gate oxide capacitance C.sub.G of a cell transistor and diffusion capacitance C.sub.DB. When the .alpha.-particle hits a storage junction node, carriers are generated along a particle track, and induce a noise current which discharges the stored charge. SER (Soft-Error Rate) is characterized by defining a critical charge Qcrit. This is the minimum charge that should be collected from the impingement of an .alpha.-particle to cause the data upset. To increase the SRAM cell tolerance of SER to the increase of the memory cell parasitic node capacitance has been recognized, and the use of polysilicon interconnection layers have been proposed.